Conventionally, in the connection structure of a semiconductor chip and a wiring substrate by the flip chip method, the reliability of the connection portion becomes one of the important problems.
As means for increasing the reliability, usually sealing resin is injected between the semiconductor chip and the wiring substrate to alleviate stress on the connection portion. The underfill method was used, as the resin injection method, in most cases, in which the semiconductor chip is mounted on the wiring substrate by the flip chip method and then liquid resin is poured and hardened (for example, Japanese Patent Laid-Open No. 2000-156386: first conventional example).
Explanations are given of the flip chip mounting method in which underfill resin is later injected according to the first conventional example, with reference to FIGS. 1A to 1C. As shown in FIG. 1A, a wiring substrate includes wiring pattern 2 formed on insulating layer 12 and solder resist 3 to cover wiring pattern 2. Generally, insulating layer 12 and wiring pattern 2 are multi-layered.
In the step of mounting the semiconductor chip, as shown in FIG. 1B, bump 5 is formed on a pad (electrode) arranged on the circuit surface of semiconductor chip 4, and the exposure portion of wiring pattern 2 on the wiring substrate and bump 5 for semiconductor chip 4 are aligned and are joined.
In the subsequent step shown in FIG. 1C, the liquid resin is injected into a space between semiconductor chip 4 and the wiring substrate and is hardened to form underfill 17 that seals semiconductor chip 4, and then a semiconductor package of the flip chip mounted structure is completed.
However, in the first conventional example in which the underfill resin is injected later, as the connection means, various techniques, such as metal diffusion junction, metal fusion junction, junction by metal content resin paste, are used. In any technique, heat is applied to the semiconductor chip and the wiring substrate during mounting. Therefore, in particular, in cases where an organic substrate is used as the wiring substrate, stress is caused by the difference between thermal expansion coefficients of the semiconductor chip and the wiring substrate and the stress is concentrated on the connection portion when the temperature lowers after the semiconductor chip has been mounted. Therefore, there are problems in that the connection portion is apt to be broken and improvement of reliability is difficult.
As another manufacturing method, a technique is proposed, in which resin is previously applied on a wiring substrate, and, during mounting of a semiconductor chip, the resin between the semiconductor chip and the wiring substrate is hardened simultaneously with the junction while bumps formed on the semiconductor chip are maintained in contact with pads formed on the wiring substrate by the application of pressure to the chip (for example, Japanese Patent Laid-Open No. 4-82241: second conventional example).
The manufacturing method in the technique according to the second conventional example is explained with reference to FIGS. 2A and 2B. First, as shown in FIG. 2A, liquid resin 17a is supplied to a position on which the semiconductor chip is mounted on the wiring substrate. Generally, an air-type dispensing device is used to supply the resin.
Then, semiconductor chip 4 on which bumps 5 are formed is adsorbed and held by chip mounting tool 18 that has adsorption hole 19, and semiconductor chip 4 is aligned with wiring on the wiring substrate. Successively, as shown in FIG. 2B, chip mounting tool 18 is moved down to make bumps 5 come into contact with wiring pattern 2 while semiconductor chip 4 is adsorbed and held. While this state is maintained, heat and pressure are applied to semiconductor chip 4 to connect the bumps and the wiring and to harden the resin between the semiconductor chip and the wiring substrate, thereby forming underfill 17. In the second conventional example, although expansion of the substrate by heat during mounting has not changed, stress, which is generated due to contraction of the substrate when it returns to room temperature, is dispersed over underfill 17. Therefore, it is possible to prevent to poor connection caused by the difference between thermal expansion coefficients of the semiconductor chip and the wiring substrate, that is, the problem in the above-described technique where the resin is injected and hardened after mounting. Further, this example is provided with the feature in which low-temperature connection is available only by contact of bumps 5 and the wiring on the wiring substrate. However, in recent years, demand for use in portable terminal devices has become severe, and it has become essential to manufacture discrete semiconductor chips that have thin profiles. A significant problem emerges in which resin climbs the chip mounting tool of the semiconductor chip mounting device while the chip is being mounted in the case of thin chips, and resin adheres to the tool.
As recent electronic devices become more sophisticated in performance and functionality, demand for higher frequencies and higher densities is steadily increasing. Particularly, in electronic device where analog circuits that generate enormous noises are incorporated, e.g., a mobile phone and a wireless LAN, and in motherboards for personal computers with higher clock speeds, noises that are transmitted to wires in the wiring substrate may cause malfunction depending on the levels of the noise. Therefore, how the noise is reduced or blocked is an important problem.
In order to reduce the effects caused by noise, a technique is used, in which power source and ground patterns are arranged in the wiring layer of a core layer and filled-in patterns that connect with the ground are arranged as much as possible in an outmost wiring layer. The example for mounting a semiconductor chip according to this conventional technique will be explained, with reference to FIGS. 3A and 3B. FIG. 3A is a plan view of the uppermost wiring layer, and FIG. 3B is a cross-sectional view of the area around the mounting portion of semiconductor chips. Bumps for semiconductor chip 4 are connected to pads 20 formed on the uppermost wiring layer and are connected with via hole lands 21 through wiring pattern 2. Also, in the uppermost wiring layer, ground patterns 2a for reducing the above-mentioned effects caused by the noise are formed in filled-in patterns. In the internal layer of the wiring substrate, writing patterns 2 that transmit signals from semiconductor chip 4 connected to pads 20 are formed, and are connected to terminals of other electronic parts through these wiring patterns in the wiring substrate. In this example, writing patterns 2 that are connected to the other electronic parts pass through the lower layer of ground pattern 2a arranged in the uppermost layer, thereby reducing the above-mentioned effects caused by the noise.
Interlayer connection for the wiring patterns in the wiring substrate having a plurality of wiring layers is performed through via hole 22. Each wiring pattern passes through the internal wiring layer by via hole 22 and is drawn to the surface layer through via hole 22 once again to be connected with the corresponding terminal of the other parts.
Also, FIGS. 4A and 4B show an example in which semiconductor chips are laminated and BGA (ball grid array) is manufactured according to the conventional mounting method. FIG. 4A is a plan view of the wiring layer of an uppermost layer, and FIG. 4B is a cross-sectional view of a conventional BGA. Similarly, to the example shown in FIGS. 3A and 3B, bumps for semiconductor chip 4 are drawn out to via hole land 21 through pad 20 and through wiring patterns 2 formed in the uppermost wiring layer, and fall to the lower wiring layer. Pads 23 for wire bonding are formed on the peripheral portion of insulating layer 12 of the uppermost layer. On semiconductor chip 4, another semiconductor chip 16 is mounted in a face-up state. Electrodes (not shown) of another semiconductor chip 16 and pads 23 are connected with bonding wires 24.
In the manufacturing method according to the first conventional example shown in FIGS. 1A to 1C, in particular, when organic materials are used as insulating layers for the wiring substrate, the thermal expansion coefficient of the semiconductor chip is approximately 2 to 3 ppm/° C. while that of the organic wiring substrate is approximately 10 to 50 ppm/° C., and a large difference exists. After the application of heat during mounting, the wiring substrate contacts more than five times that of the chip, and thus much stress concentration is produced in the junction portion. This stress concentration causes problems of various junction breakages, i.e., breakage between bumps formed on electrodes on the chip and electrodes, breakage of electrodes, connection interface breakage between bumps and pads on the wiring substrate, and the stress concentration also caused a problem in which reliability is lowered. Further, since these failures are caused by the difference between the thermal expansion coefficients, the rate of failure occurrence tends to increase in large chips; in particular, it is very difficult to apply this example to a large chip having a peripheral structure in which bumps are arranged only in the periphery of the chip.
Next, the problems in the manufacturing method according to the second conventional example shown in FIGS. 2A and 2B will be explained. In this method, expansion of the substrate by heat during mounting has not changes. However, during mounting the semiconductor chip, stress caused by contraction of the substrate when it returns to room temperature is spread by the resin because the resin is hardened while the chip is being held by the chip mounting tool. Therefore, the connection failure caused by the difference between the thermal explosion coefficients of the semiconductor chip and the wiring substrate, i.e., the problem in the above-mentioned method in which the resin is injected after mounting, can be prevented. However, in recent years, demand for semiconductor devices having thin profiles for use in portable terminal devices has become severe, and it has become essential to manufacture discrete semiconductor chips that have thin profiles. As chips are thinner, the problem becomes obvious, that resin climbs the chip mounting tool of the semiconductor chip mounting device during mounting and adheres to the tool. This causes a problem that, while the resin previously applied on the substrate is pushed out during the steps of applying pressure and heat to the semiconductor chip and leaks out to the periphery of the chip, the resin climbs from the side surfaces of the chip and is in contact with the heated tool of the mounting device that adsorbs the chip and applies pressure to the chip, so that the resin becomes hardened, and then mounting after the next time becomes impossible.
The reason why this problem occurs is explained with reference to FIG. 5, which is a schematic view of a state in that a thin chip is adsorbed by the chip mounting tool. Chip mounting tool 18 is designed to be sufficiently smaller than semiconductor chip 4 taking into consideration cases where the resin climbs the top surface of semiconductor chip 4 by variations in the amount of discharge. However, in cases in which the thickness of semiconductor chip 4 is sufficiently thin, as shown in FIG. 18, and the chip mounting tool is smaller than the formation portion of bumps 5, there occurs a problem that the chip is broken when pressure is applied to semiconductor chip 4 by chip mounting tool 18. Therefore, for thin chips, chip mounting tool 18 must be made large so as to cover at least bumps 5, and the possibility is significantly increased, that resin that climbs up the top surface of the chip adheres to the chip mounting tool and becomes hardened.
Further, because the chip is thin, it is easy for the resin to climb, and therefore variations in the amount of resin that is discharged must be reduced to a fixed limit. It is generally known that when the thickness of the chip is 15 mm or less, controlling the amount of resin is difficult, in case of liquid resin, and reducing variations in the amount of resin that is discharged becomes difficult.
In terms of preventing the resin from adhering to the chip mounting tool and of controlling the proper amount of resin, film-shaped resin is proposed, and various resin materials, such as thermosetting, thermoplastic, and thermosetting and thermoplastic mixture resin materials, are being studied. However, film-shaped resin materials used for underfill are burdened with many problems peculiar to film shapes, for example, adhesive suitability when film-shaped resin adheres to the wiring substrate, the generation of bubbles, and connection reliability after hardening. These film-shaped resins have problems in that not only are they still under development, but material costs are also very expensive. Further other problems that occur when film-shaped resin materials are used is that conventional resin dispensing devices cannot be used and that capital investment must be made for new film adhering device, and this means there is the difficulty in reducing the manufacturing costs.
Next, structural problems are explained about electronic devices manufactured according to the conventional mounting method. In the conventional chip mounted structure in which parts for substrate surface layer wires are mounted, as shown in FIGS. 3A, 3B, 4A and 4B, many signal lines must fall in the wiring layer of the internal layer, and surface layer wires and internal layer wires are connected through via holes for interlayer connection. Therefore, though a general semiconductor chip with several hundreds of pins is mounted, an enormous number of via holes is required. Particularly, as the conventional example shown in FIGS. 3A and 3B, when the ground patterns are formed in the uppermost layer of the substrate in order to address higher frequencies, this becomes more significant, and almost all of the signal lines must fall in the internal layer.
Here, a via hole land diameter in the order of 200 μm is required in the leading-edge. As the number of via holes is increased, the area occupied by the via holes is increased. Therefore, it is very difficult to route wires because the wiring area is limited and alternative wiring is needed, the number of wiring layers must be increased in some cases, and the wiring length is further increased. Accordingly, to be able to use higher frequencies, it is necessary to minimize the number of via holes.
Further, since the increase in the number of via holes causes an increase in the rate of occupation in the via hole arrangement area and the wiring area in the uppermost layer, this causes many constraints on mounting intervals between parts and has harmful effects on the higher-density mounting of parts. For example, in BGA shown in FIGS. 4A and 4B, since bonding pads are arranged away from semiconductor chip 16, the bonding wires become longer and packaging in a chip size becomes difficult.
Also, concerning costs, via holes are formed one by one in the insulating layer by laser or the like in many cases, because the number of processes is increased in proportion to the increase in the number of via holes, as a matter of course, and therefore production costs for substrates increase. The increase in the number of layers significantly causes an increase in costs.
On the other hand, in terms of reliability, via holes are portions that are apt to be broken in the substrate. In terms of quality such as production variability, it is more preferable to have a smaller number of via holes. An increase in via holes becomes weakens to reliability.